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So you're essentially creating a source synchronous output. That generated clock should be after derive_pll_clocks in your file. Also, I don't see the output port name anywhere. Is it clk100? And you were missing get_pins for the -source argument. Here's what you should have:
create_clock -name CLK1 -period 20.0
create_clock -name CLK2 -period 20.0
derive_pll_clocks
create_generated_clock -source {get_pins pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk} -multiply_by 1 {get_ports <output port name>} -name clk100
derive_clock_uncertainty
set_false_path -to {get_ports <output port name>}
set_output_delay -clock -max 6.000
set_output_delay -clock -max 6.000
set_output_delay -clock -max 6.000
set_output_delay -clock -min <value>
set_output_delay -clock -min <value>
set_output_delay -clock -min <value
The extra generated clock is not creating the 100 MHz clock, so you can't have "-multiply_by 2 -duty_cycle 50.00" in that constraint. That's up to your PLL. Multiply by 1 is used because the clock at the output port of the device is the same as the clock output from the PLL. Timing analysis takes care of the delay between the PLL output and the output port.
See this online training for more details:
https://www.altera.com/support/training/course/ocss1000.html --- Quote End ---
sstrell,
yes it should be a source synchronous output/input. I have an extern device with a 32 bit data word coming into fpga and fpga outputs data to it. The fpga acts essentially as FIFO.
I put generated clock now after derive_pll_clocks in my file. Also I added now the output port name which is pclk (see attached thumbnail view of RTL viewer)
https://alteraforum.com/forum/attachment.php?attachmentid=15539&stc=1 I also tired to implement the source clk in the create_generated_clock command:
create_generated_clock -source {get_pins pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk} -multiply_by 1 {get_ports pclk} -name gclk100
However still no success and compiler left me with same warnings:
Warning: Ignored filter at SDC1.sdc(18): get_ports could not be matched with a port
Warning: Ignored filter at SDC1.sdc(18): get_pins could not be matched with a port or pin
Sorry but at this point I'm at my wits end. I searched in RTL viewer and in Technology Map viewer (post fitting) for the pll divclk pin and it really is there. (see attached picture).
But in RTL viewer divclk is not found. There it is just outclk of the pll.
https://alteraforum.com/forum/attachment.php?attachmentid=15541&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=15540&stc=1 After the pll I connected the ALTDDIO. There is the net CLK_100 between them. And after ALTDDIO there is the output port of the top_level modul.
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