Strange PLL Clock causing me failing paths in cyc V design

So you're essentially creating a source synchronous output. That generated clock should be after derive_pll_clocks in your file. Also, I don't see the output port name anywhere. Is it clk100? And you were missing get_pins for the -source argument. Here's what you should have:

create_clock -name CLK1 -period 20.0 
create_clock -name CLK2 -period 20.0 
derive_pll_clocks
create_generated_clock -source {get_pins pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk} -multiply_by 1 {get_ports <output port name>} -name clk100
derive_clock_uncertainty
set_false_path -to {get_ports <output port name>}
set_output_delay -clock  -max 6.000 
set_output_delay -clock  -max 6.000 
set_output_delay -clock  -max 6.000 
set_output_delay -clock  -min <value> 
set_output_delay -clock  -min <value> 
set_output_delay -clock  -min <value 

The extra generated clock is not creating the 100 MHz clock, so you can't have "-multiply_by 2 -duty_cycle 50.00" in that constraint. That's up to your PLL. Multiply by 1 is used because the clock at the output port of the device is the same as the clock output from the PLL. Timing analysis takes care of the delay between the PLL output and the output port.

See this online training for more details:

https://www.altera.com/support/training/course/ocss1000.html