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You have clk_100 as a virtual clock. If it is actually an output clock, you need create_generated_clock at its output clock port (port is a top-level pin in SDC terminology; pin in the input or output of a cell) with the source as the output pin of the PLL and a false path to that output port as well so the path doesn't get analyzed as a data path.
You also need set_input_delay constraints and matching -min set_output_delay constraints.
As for the warning about dual clocks on one of the inputs, you'll have to look at/post the clocks report to see what's going on there.
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Ok, I tried to create generated clock, but have trouble matching the right ports:
create_clock -name CLK1 -period 20.0
create_clock -name CLK2 -period 20.0
create_generated_clock -source {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|outclk} -multiply_by 2 -duty_cycle 50.00 -name {clk100} # <---- Create generated clock command
derive_pll_clocks
derive_clock_uncertainty
set_output_delay -clock -add_delay -rise -max 6.000
set_output_delay -clock -add_delay -rise -max 6.000
set_output_delay -clock -add_delay -rise -max 6.000
The log is telling me that
Warning (332174): Ignored filter at SDC1.sdc(5): pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|outclk could not be matched with a port or pin or register or keeper or net or combinational node or node
Warning (332049): Ignored create_generated_clock at SDC1.sdc(5): Argument -source is not an object ID
And fitter is then ignoring my set_output_delay commands.
I don't exactly know which output port of my pll I have to use for -source.
I tried
- pll_inst_100|pll_100_inst|altera_pll_i|outclk
- pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|outclk
- pll_100:pll_inst_100|outclk_0
but none is working. Always console say that it could not be matched with a port.
If I am properly informed I can choose my own name for the -name field? Do I have to set a target?
When fitter ignores the create_generated_clock command because of wrong fields but then fitter is using derive_pll_clocks and creating the clock on its own:
Info (332110): Deriving PLL clocks
Info (332110): create_generated_clock -source {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|refclkin} -multiply_by 6 -duty_cycle 50.00 -name {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|vcoph} {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~FRACTIONAL_PLL|vcoph}
Info (332110): create_generated_clock -source {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|vco0ph} -divide_by 3 -duty_cycle 50.00 -name {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk} {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk}
When I then use
pll_inst_100|pll_100_inst|altera_pll_i|general[0].gpll~pll_output_counter|divclk in my set_output_delay statements clock field fitter seems to set the output delays accordingly. At least he is not ignoring the delay output commands.
But still failing path with this message:
Slack______From Node ____________________________________ ____to Node __________Launch Clock ___________________________________________________________________________________________Latch clock____Relationship __Clock Skew ___Data Delay
-3.890 io_control:io_control_inst1|data_out dq pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk 10.000 -4.949 2.861
Do I need to false path between this same used clock ?
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