Strange behavior with On-chip Mem

sstrell,

The slave component is a generic On-Chip Memory RAM: 2-Port, exported from the Quartus IP Catalog.

With two read/write ports,

Q_a output as 64-bit words,

Depth is 512 words,

Auto memory type,

Single Input clock,

No byte enable or read enable,

Registered read output ports q_a and q_b

Asynchronous clear supported,

Don't care on mixed port read during write,

Same port read during write is new data,

Initialize to blank.

As you can see all the settings are normal. The read is one cycle before incrementing the state.

Would it be a problem ifthe source address is registered? After State_1, the address is derived from a register. Still I don't see why there's a two cycle delay.

On the Avalon-MM Master, the following is given. It seems to be the address port that is causing the problem:

registers

wires

The actual verilog code:

assign avm_srt1_address = f_find_op_inb ? node_pnt_inb * 10 + node_offset_inb : avs_s1_address[4 +:9 ] * 10+ avs_s1_address[3:0];

assign avm_srt1_read = f_find_op_inb ? 1'b1 : avs_s1_read; // seems to have no affect on the delay

assign avm_srt1_write = f_find_op_inb ? 1'b0 : avs_s1_write; // seems to have no affect on the delay

assign avm_srt1_writedata = avs_s1_writedata[63:0]; // seems to have no affect on the delay

assign node_pnt_inb = {row_pnt_inb, column_pnt_inb[5:0]};

assign column_pnt_inb = check_hit[5:0];

check_hit = (!skip_array[ 0 ] & (target == search_string[ 0 ])) ? {1'b1, 8'd 0 } :

(!skip_array[ 1 ] & (target == search_string[ 1 ])) ? {1'b1, 8'd 1 } :

(!skip_array[ 2 ] & (target == search_string[ 2 ])) ? {1'b1, 8'd 2 } :

(!skip_array[ 3 ] & (target == search_string[ 3 ])) ? {1'b1, 8'd 3 } :

(!skip_array[ 4 ] & (target == search_string[ 4 ])) ? {1'b1, 8'd 4 } :

(!skip_array[ 5 ] & (target == search_string[ 5 ])) ? {1'b1, 8'd 5 } :

9'b0;

...

always @ (posedge csi_clock_clk or posedge csi_clock_reset)

begin

if(csi_clock_reset)

begin

...

end

else

begin

case (state)

......

STATE_INB_IDLE:

begin

node_offset_inb <= '{default:0};

row_pnt_inb <= '{default:0};

......

STATE_READ_NEXT:

begin

node_offset_inb <= node_offset_inb +1;

row_pnt_inb <= row_pnt_inb +1;