Strange Behavior when using case statement on EPM3128A

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY USBDownloader IS
    GENERIC (
        CLK_DIVIDER_6 : integer := 20000000  --------DO NOT CHANGE--------
        );
    PORT (
----------------------CLOCKS--------------------------------------  
        SYS_CLK_IN : IN  std_logic;
        CLK_6MHz   : OUT std_logic;
        ULED       : OUT std_logic;
        RLED       : OUT std_logic
        );
END ENTITY USBDownloader;
ARCHITECTURE rtl OF USBDownloader IS
    TYPE case_counter_type IS (a, b, c);
-- Declare Constants and Variables 
    SIGNAL CLK_TEMP_6 : std_logic                   := '0';
    SIGNAL CNT_6      : integer RANGE 0 TO 20000000 := 0;
    SIGNAL case_counter : case_counter_type := a;
    SIGNAL uled_r : std_logic := '1';
    SIGNAL rled_r : std_logic := '1';
    
BEGIN
-------------------------------------------------------------------------------
    
    PROCESS (CLK_TEMP_6)
    BEGIN
        IF rising_edge (CLK_TEMP_6) THEN
            CASE case_counter IS
                
                WHEN a =>
                    
                    uled_r       <= '0';  ----GREEN LED ON-----
                    reld_r       <= '1';
                    case_counter <= b;
                WHEN b =>
                    uled_r       <= '1';
                    rled_r       <= '0';  -------RED LED ON-----
                    case_counter <= a;
                WHEN OTHERS =>
                    NULL;
            END CASE;
        END IF;
    END PROCESS;
    PROCESS (SYS_CLK_IN)
    BEGIN
        IF (SYS_CLK_IN'EVENT AND SYS_CLK_IN = '1') THEN
            CNT_6 <= CNT_6 + 1;
            IF (CNT_6 = CLK_DIVIDER_6-1) THEN
                CLK_TEMP_6 <= NOT CLK_TEMP_6;
                CNT_6      <= 0;
            END IF;
        END IF;
    END PROCESS;
    CLK_6MHz <= CLK_TEMP_6;
-------------------------------------------------------------------------------
    ULED <= uled_r;
    RLED <= rled_r;
    
END rtl;