Strange - counter counts without clock

As a first step, look at the gate level netlist (Technology Map Viewer) to understand how the logic is actually implemented.

You'll notice that the 7493 3-bit block (QB..QD) is synthesized as a synchronous counter, in contrast to the original 7493 ripple counter. The combinational logic is implemented in a single logic cell.

The glitch occurs at a time when all three counter flip-flops change state. If more than one input of a LUT (logic element) changes state simultaneously, output glitches can occur. If it really happens depends on arbitary routing and LE internal delays. See http://www.alteraforum.com/forum/showthread.php?t=26151 or similar previous threads.

That's why the shown design style must be considered unsafe.