Forum Discussion
New ContributorStill cannot assign LVDS signal to MAX-V device
I try your suggestion. I have a single-ended signal call OUT_P and assigned it as LVDS_E_3R, the pin planner created the corresponding diff signal call OUT_P(P).
When I compile it, Quartus returns a pop-up problem report window.
The short version of the Preview of the report :
Problem Details
Error:
Internal Error: Sub-system: FYGR, File: /quartus/fitter/fygr/fygr_cdr_op_place.cpp, Line: 1882gid != DEV_ILLEGAL_GLOBAL_IDFitter pre-processing
Stack Trace: ....................................
................................
Executable: quartus_fit
Comment:
None
System Information
Platform: windows64
OS name: Windows 10
OS version: 10.0
Quartus Prime Information
Address bits: 64
Version: 17.1.0
Build: 590
Edition: Lite Edition
14 Replies
TChin5Attached is the archive file. I have to change the file extension to text otherwise I can't upload it. (the Answer button gets gray out when it is of type ".RPT")
I have already tried Quartus 18.1 with no luck.
I choose LVDS_E_3R because MaxV only support this.
The file was able to compile when I change only this pin to another I/O standard but fail when I change it back
AbeFrequent Contributor
Can you archive your project and post it here.. let us check it out.. Maybe you can also download the latest 18.1 version and try in the meantime.
