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Altera_Forum's avatar
Altera_Forum
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18 years ago

std_logic_vector vs array

Here is my question.... Are these two equivalent? 1. signal sig_name : std_logic_vector(0 to 511)(7 downto 0); 2. type sig_name_array is array 0 to 511 of std_logic_vecto...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

looking in some VHDL references I have, it does say that unconstrained arrays are not possible in entities.

So I think the method you suggest is the best option....get it into a 1-D format.

Alternatively, perhaps, put the array into a memory block??