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Altera_Forum's avatar
Altera_Forum
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18 years ago

std_logic_vector vs array

Here is my question.... Are these two equivalent? 1. signal sig_name : std_logic_vector(0 to 511)(7 downto 0); 2. type sig_name_array is array 0 to 511 of std_logic_vecto...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

i've done a lot of VHDL and have never seen 1. being used.

Usually 2. but (511 downto 0) instead of 0 to 511?

generally

type type_name is array (range) of element_type;

Hope that helps