Altera_Forum
Honored Contributor
14 years agosram read and write
i am trying to alter the data stored(by control panel) in sram .i wrote the vhdl program to alter the data and i am reading with control panel to see if it is changed...my problem is every time i am reading only "1" on the data pins...i learnt that before reading the datawe need to put the biderectional data pins in high impedance state.i tried that also...my program is
LIBRARY ieee ; USE ieee.std_logic_1164.all ; use IEEE.std_logic_unsigned.all; entity abc is port(clk:in std_logic; --Input from FPGA switches din:inout std_logic_vector(15 downto 0); -- Data outputs/inputs from/to SRAM from/to FPGA ceo,oeo,weo,lbo,ubo:out std_logic; --Inputs to SRAM from FPGA addr:out std_logic_vector(17 downto 0)-- Address inputs to SRAM from FPGA ); end; architecture abcd of abc is begin ceo <= '0'; oeo <= '0'; lbo <= '0'; ubo <= '0'; process(clk) variable temp_addr:std_logic_vector(17 downto 0) :="000010101011001010" ; variable temporary: std_logic_vector(15 downto 0); variable count,flg:integer range 0 to 100:=0; begin if clk'event and clk = '1' then if (count<=10) then if flg = 0 then flg:= 1; end if; if flg = 1 then din <= (others => 'Z'); addr <= temp_addr; weo <= '1'; temporary := din; flg := 2; end if; if flg = 2 then temp_addr:=temp_addr+1; weo<='0'; din <= temporary and x"10ff" ; flg := 0; count := count+1; end if; end if; end if; end process; end; can anybody please help me find the problem