SRAM model Generation

What is the difference between the following code and the real sar controller?

--- Quote Start ---

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

entity sram1024kx8 is

port (A : in Std_logic_vector(19 downto 0);

D : inout Std_logic_vector(7 downto 0);

nCE : in std_logic;

nCE2 : in std_logic;

nWE : in std_logic;

nOE : in Std_logic);

end;

architecture Behaviour of sram1024kx8 is

subtype Byte is Std_logic_vector(7 downto 0);

type Mem is array (0 to 1048576 ) of byte;

signal Memory: Mem := (others => Byte'(others=>'U'));

begin

process(A, D, nCE, nCE2, nWE, nOE)

begin

D <= (others => 'Z');

if nCE='0' and nCE2='0' then

if nOE = '0' then -- Read operation

D <= Memory(To_Integer(unsigned(A))) after 10 ns;

elsif nWE = '0' then -- Write operation

Memory(To_Integer(unsigned(A))) <= D;

end if;

end if;

end process;

end;

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Please I can't get the relationship between the both I thought it was enough ?

Do you have an example so that I could based on this ?