Forum Discussion
Altera_Forum
Honored Contributor
15 years agoSRAM model Generation
Hello I have a NIOSII system as follow : EPCS controller CPU - tristate-Bridge - sram_ctrl_v00 + some other bits my SRAM is external to the FPGA. So I have created a controller sra...
Altera_Forum
Honored Contributor
14 years agoHello
The model need to be included in the file that represent your NIOS (at the bottom of the file). You will find locations where you can include your code : -- <Altera_Note>..... The code will not be removed when you re generate your NIOS II system. This is the idea. To check my design , I had no time to perform what is described above, but this is the philosophy. Instead , I have used the internal memory under Modelsim , and use SDRAM in the real product. This was to be able to check a full design (NIOS + Logic) together. Also , you will have to set the NIOS II software/BSP (under Eclipse) to generate the correct file for SDRAM or Internal Mem. Ben