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Altera_Forum
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14 years ago

SRAM model Generation

Hello I have a NIOSII system as follow : EPCS controller CPU - tristate-Bridge - sram_ctrl_v00 + some other bits my SRAM is external to the FPGA. So I have created a controller sra...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hello ,

Please I am facing the same problem can you give me some advice on interfacing external memory:

I wrote a memory model+testbench+controller

How should I move forward?

I would appreciate any advice...