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Altera_Forum
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16 years ago

SRAM interface timing discrepancy from Quartus-II 7.0 and 9.0

I have a design which contains an SRAM interface with the default PLL phase shift, -4.8ns for this SRAM. It was compiled by Quartus-II 7.0 and it works perfectly on my target board with an EP2C20F484...
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Altera_Forum
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16 years ago

Kaz,

Thank you very much for your reply. I am trying to find what causes timing discrepancy.

I agree with you on tco,pd, and tsu assignments. Although the slightest change of code means a different fitting, a few examples show that timings only change very slightly from the same compiler, e.g. Quartus-II 9.0 SP1. However, you can't assign tco, th, tpd and tsu to every path although the values of every path can be reported. Sometimes, the compiler creats warning meassages such as "no timing path applicable to specified source and destination". I think that this applies to the paths from the SSRAM interface clock to the SSRAM interface outputs.

BC