Honored Contributor
Honored ContributorIt is all pointing to unstable timing window. It is difficult to blame the tool. You may blame the build after each compilation. Even the slightest change of code means a different fitting. In particular you need to check the actual Tco at your output pins in the timing report. These could vary from build to build. especially so if you are not using fast io registers. You must constrain Tco, even though you get what you want or better but no fixed values. You must also constrain Tsu,Th of inputs which should be fast registers.
It is hard to measure PLL phase and say there is a difference of 2ns from version to version. PLLs may go wrong of course but needs proof. The issue of temperature is to test the fpga/sram timing over a good range of operation. You will also need to check several boards. If you are reading and writing to sram on same clk then there is the added complexity of clk/data direction being either together or opposite.
