Honored Contributor
Honored ContributorI am also trying to get an I2S interfacing working with an A/D chip.
I am using a Cyclone III FPGA, and need to interface to I2S channels that have multiple A/D chips cascaded. I thought Altera would have some pre-made interfaces that would work for this as the concept of clocking in the data is pretty straight forward, but I am not having much luck. I was trying to use a simple shift register to clock in a channel serially then read it out in parallel, but I am new to the NIOS core interface methods and am not making much progress at setting this up. I was quite familiar with Lattice tools using ABEL, but unfortunately I am getting up to speed with Altera with the graphic design but looking at the verilog where required at the same time as this project, my design is going way to slow. Any tips would be appreciated. Thanks, Dale
