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SK_VA's avatar
SK_VA
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

SPI Slave Timing Constraints

Hi, I have an SPI slave implemented in FPGA with input SCLK clock ranging between 10-20MHz. I have added two flop synchronizer for all SPI input signals CS,SCLK,MOSI before using them in the Slave ...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


You have to constrain the virtual clock that connect to the clock pin of the source data signal.


Thanks

Best regards,

KhaiY


KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

Best regards,

KhaiY