Forum Discussion
SK_VA
Occasional Contributor
Occasional ContributorSPI Slave Timing Constraints
Hi, I have an SPI slave implemented in FPGA with input SCLK clock ranging between 10-20MHz. I have added two flop synchronizer for all SPI input signals CS,SCLK,MOSI before using them in the Slave ...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi,
You cannot set false path if you want to know the timing relationship between the signals. To constrain a source synchronous interface, you may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an433.pdf
Thanks
Best regards,
KhaiY
SK_VAOccasional Contributor
Occasional ContributorHi,
Thanks.
I am using a two flop synchronizer that runs at a higher frequency for all the SPI slave inputs including clock. Do I need to constrain with a virtual clock of higher frequency or wrt spi slave clock input as source synchronous.
