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Altera_Forum's avatar
Altera_Forum
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8 years ago

SPI Slave Timing Constraint Question

Hi, I have designed an spi slave component and am having problems working out the best/correct way of creating timing constraints for the interface. A quick description of my component: Th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Actually an SPI slave where all the inputs are synchronised with a double register-chain doesn't need to be constrained. The

set_false_path -from  -to *
will do. As the miso is clocked by a higher frequency clock a 
set_false_path _from * -to miso
is OK too.

The same reasoning applies for the case of an SPI Master (reversing the directions of the false paths)