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Honored Contributor
Honored ContributorSPI Slave Timing Constraint Question
Hi, I have designed an spi slave component and am having problems working out the best/correct way of creating timing constraints for the interface. A quick description of my component: Th...
Altera_ForumHonored Contributor
Honored ContributorHi James,
Why are you not using the sclk to clock your data ? This clock is synchronous with your other signals and you will not have to add the double registers. In this case, your constraint file will be very simple. Jerome
