speed up read of embedded RAM from external bus interface

You are probably doomed to fail.

To avoid metastable issues you need to synchronise the address lines to the fpga's clock. This requires at least one additional clock delay that you haven't allowed for.

This means that you actually need to generate a 60MHz clock on the fpga that is phase synchronous with the 60MHz EBI clock, and then use that clock to latch the addresses into the internal memory block.

Doesn't help you find the latch in the read data path though.

Are you sure your problem isn't an additional latch in the addresses?