Forum Discussion
LFrin
Occasional Contributor
Occasional ContributorSpeed Transceiver-Channel near PCIe Hard IP Blocks
Hello, I use the FPGA Cyclone V GT "5CGTFD7C5F23I7N". I'm wondering if the speed of the transceiver channels next to the PCIe Hard IP Blocks is limited? Can these channels also be used as 5 Gbps tr...
SengKok_L_Intel
Regular Contributor
Regular ContributorYou can refer to the following PCIe avalong ST user guide, page 52 to understand the Channel placement and limitation.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_c5_pcie_avst.pdf
The answer should be "You can assign other protocols to unused channels the if data rate and clock specification exactly match the PCIe configuration"
Regards -SK
