Speed grades and internal timings

Looking at the help for this function:

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Notes: When the altclkctrl megafunction is used to select between two or more clocks, the Timing Analyzer issues a gated clock warning message. The Quartus II software takes into account the additional clock skew during timing analysis.

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...technically I guess is a gated clock but done in such a way that Quartus can correct for it. There may be some specialised silicon to perform this function, which is well characterised. I think that the problem with gating a clock with any old gate, is the predictability of that gate's propagation delay and the routing delay associated with it. With this megafunction, those delays may be tied down much more tightly.

I'm guessing as I haven't used it before; but you could raise a question on the Altera Mysupport. Not sure if Rysc could offer any peals of wisdom.