Speed grades and internal timings

Many thanks to both of you for the responses.

Just one more thing:

Perhaps I have misinterpreted the meaning of 'gated clock' but would using using the altclkctrl megafunction be considered clock gating?

I am using this megafunction in my current design to 'gate' a clock used to program a clock generater. The reason is to disable the clock once the generator is programmed after reset to save power. I saw in the timing simulation that the output of this buffer was skewed. I also recieved a warning in quratus saying :

"found 1 node in clock paths which may be acting as ripple and / or gated clocks --nodes analyzed as buffer(s) resulting in clock skew. "

Is it possible to use this megafunction and not recieve this warning? In my design, I am ignoring this warning (which I assume is safe to do) as it is only used to program the generator before being disabled.

My current design is synchronous, but thank you for the info on the DCFIFO, I hadn´t been aware of it before. After having a read in the handbook it seems as though it could be quite useful in some situations. My next project is to do some work on an old design which controls a VME Bus. From my initial research it looks horrible with the asynchrounous aspect, but certainly the information given here should help me out in the future with it.

Thanks again.