Forum Discussion
Altera_Forum
Honored Contributor
18 years agoSpeed grades and internal timings
Hi, Not so much a problem that I´m having just more something I would like to understand better. I am currently using a Stratix II GX I-Grade -4 FPGA for a project. I am using Modelsim to ca...
Altera_Forum
Honored Contributor
18 years agoRysc makes some good points there and the distinction between asynchronous designs and synchronous ones is important - I've not bothered with timing simulations because all of my designs in recent years have been deliberately synchronous. If you're doing asynchronous design, Ardni, then pay close attention to what Rysc is saying - his posts are really on the ball here!