Speed grades and internal timings

Just to clarify, in my previous post I was talking about simulating in Modelsim (I've never used the Quartus simulator). Reading the bit of the Quartus manual which describes simulation in Modelsim:

--- Quote Start ---

You do not have to choose from the Delay list because the

Quartus II EDA Netlist Writer generates the SDO using the

same value for the triplet (minimum, typical, and

maximum timing values). The value is derived from either

the fast (minimum) timing model or worst case (maximum)

timing model, depending on which timing model was used

in the last timing analysis. In the standard compilation

flow, the Quartus II software writes the SDO using timing

values from the worst case (maximum) timing model.

--- Quote End ---

Like I said it's been a while since I've done this (I've usually found it to be not necessary) but if you're simulating in Modelsim then you should ensure that you select the timing model you want when you run the compilation in Quartus (back when I did this last you could still select max, min or typ in Modelsim).

If you gate a clock then you can muck up the timing analysis because you're adding in a delay on the clock reaching some registers relative to others.

Instead of using a gated clock use a clock enabled register:

process(clk)
begin
    if rising_dege(clk) then
        if clk_enable = '1' then
            -- put your code in here
        end if;
   end if;
end process;

There's some discusison of this in the Altera coding standard document.

Passing signals between clock domain depends on the application. If you've got one signal or several signals which are unrelated then you can simply do what you described with one or two synchonising registers. If for example you're passing a data bus across clock domains then you need something a bit more clever to ensure that the dta doesn't get corrupted (i.e. you don't want some of the bits appearing on the opposite side a clock cycle earlier or later than the others otherwise you'll end up with corrupted data). In this case you would need to do something clever with handshaking like a FIFO sort of structure - this takes several clock cycles to get the data across but prevents corruption - e.g. freeze the data in the old domain and synchronise the "frozen" signal in the new domain; latch the data into the new domain and acknowledge this back to the old domain; synchronise the acknowledgement in the old domain and then unfreeze the data.

This is obviously more complex so you need to think about what you want to do, but there's probably a megwizard thing to hekp you do it.

Good luck