Speed grades and internal timings

Hi again, Many thanks for the reponses.

Just one or two final things I´m not 100% on:

How can i switch between the max and min models in a timing simulation in Modelsim. I´ve been looking at it for some time now, but I don´t see where I can choose.

Also, what are the advatages of simulating the max and min models. Is it ever nessesery to simulate with the min model? I know people have been put forward the argument that timing simulations are not nessesery and its something I hope not to do in my next project, but for the moment I´m curious to understand a little more about them.

Finally when Rysc mentioned 'don't gate clocks' and 'be careful when transfering data between clock domains' could someone (or Rysc if you are reading) please expand just a little. I know its probably for another thread but I´m aware that probably I have done some things that maybe I shouldn´t as regards my coding style. I am gating 1 clock in my design and also in many cases I am passing signals between clock domains.

Why should clocks not be gated? and what is the alternative?

What precautions should be taken when passing signals between clock domains? Is it enough to pass them through 2 flip flops?

I really appreciate the help you guys give, so thanks again.