Speed grades and internal timings

There is no typical, just min and max, which are two separate models(and significantly different). For coding styles, just try to minimize clock domains, don't gate clocks, be careful when transfering data between clock domains, and use the asynchronous set/reset for domain resetting only(i.e. don't use it like logic). I know that's brief, but it depends on your system and requirements on what can be done. (I've worked on some systems with ~100 clock domains, huge clock muxes in logic and all sorts of yucky stuff. They had to do all this for what the system did, and they did everything through RTL sims and timing analysis, so it's definitely possible.)

I would double check what your timing sim showed you compared to the RTL sim(and/or static timing analysis). Note that nothing goes "unkown" in a real device, besides metastability events which would show up in static timing analysis. So it's worth investigating what your timing sim is showing you and figuring out what it means in hardware.