Speed grades and internal timings

Altera have a document on coding style:

http://www.altera.com/literature/hb/qts/qts_qii51007.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=coding%20style

Most of the FPGA manufacturers seem to produce a similar document and on the whole they pretty much agree.

You can select between best and worst case timing models in the simulator GUI. It's a while since I've done it myself but if memory serves me correctly then the simulators tend to give you a choice between min, typ and max timing constraints - for Altera min and max are the same (worst case) and typ is obviously typical. Perhaps somebody could correct me if this is wrong or out of date information.

(I usually find it takes to long and isn't necessary unless you find a problem - just do a really good RTL simulation with a comprehensive testbench and make sure that you apply timing constraints to the place and route - let Quartus do the work for you)