Speed grades and internal timings

Thank you for your reply Rysc.

When using modelsim for the timing simulation I include the.sdo file. But does this file contain both the fast and slow model? or how can I switch between them? I assumed by default I would be simulating the worst case (slowest).

Generally it would be more useful to do a simulation using the slow model I am thinking, but what would be the advantages of simulating the fastest model? To investigate hold times etc? but I suppose they are presented in the static timing analyses?

I did read about quite a few people saying that they haven´t been doing timing simulations recently and too be honest it takes so much time to do them properly that I´m kinda glad to hear that it may be be totally nessesery. I have a work mate who swears by them, so I have also been doing them. I have spotted several things in the timing simulations that I didn´t see in a functional simulation or in the static timing analyses. Things like signals going undefined, when I change them from within in a state machine. Sometimes when I alter a signal in one state it does not work (i.e. goes undefined), but if I alter the code to change the signal in a different state,it works. Anyway I don´t understand well, but its something I had been meaning to ask here, but perhaps its for a different thread. Perhaps its something to do with my coding style.

Do you have any links to the 'synchronous design practices' that you mentioned in your last thread? I´d be interested to have a read.

Also I am still using the classic timing analyser in Quartus, but for my next project, I plan on switching to Timequest. Perhaps when you mentioned that its possible to get away without doing timing simulations you had in mind that I would be using timequest with the entire design contrained? Unforunately this is not the case, but from reading quite a bit on this forum recently, I see almost everyone is using Timequest, so hopefully in the near future, I can make the change too.

Thanks for your help