Forum Discussion
Altera_Forum
Honored Contributor
13 years agoI've seen the datasheet of the FPGA, and it says that voltage accepted by the pins depends on the duty cycle of the signal (DC 4.0V, 10% duty Cycle 4.5V).
I dont see the minimun voltaje level for a HIGH, but If it dont work I'll just decrease the serial resistor to get more than 2.5V Thanks for the advice