specifications of external clock signal DE2 Board and Starter Development Board

Look at the schematic for the DE2. I just looked at an old printed copy and the external clock SMA connector is followed by a 1k pull-down and then goes directly to an FPGA pin.

If you have the clock source close to the board, then you could put a 1k series resistor between the clock source and the DE2 board. That external 1k and the on-board 1k would create a voltage divider, resulting in a clock signal with a peak of about 2.5V on the FPGA pin - this assumes that you do not have much ringing though - so check with an oscilloscope. If you look in the handbook you will find there is a specification for ringing/overshoot. So long as you're under the handbook values, you will not damage the FPGA clock input pin.

Cheers,

Dave