Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

source synchronous interface or virtual clock?

My FPGA is connected to an ADC. There are three interface signals between them : SCLK and DOUT, which are outputs from FPGA, and DIN, input from ADC. SCLK is generated by dividing the system c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Indeed I was wondering why set_clock_latency doesn't take effect on my generated virtual clock. Now I see the point.

Thank you, Rysc!

I am reading your source-synchronous wiki document. Good material. It helps me have a deeper understanding of timing constraint on this kind of interface.Thanks again!