Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorsource synchronous interface or virtual clock?
My FPGA is connected to an ADC. There are three interface signals between them : SCLK and DOUT, which are outputs from FPGA, and DIN, input from ADC. SCLK is generated by dividing the system c...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Since you're sending a clock to the ADC and getting back data, it is source-synchronous, --- Quote End --- I thought 'source synchronous' meant that the data and the clock are travelling in the same direction, i.e. one receives the sending clock along with the sent data?
