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Altera_Forum
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14 years ago

source synchronous interface or virtual clock?

My FPGA is connected to an ADC. There are three interface signals between them : SCLK and DOUT, which are outputs from FPGA, and DIN, input from ADC. SCLK is generated by dividing the system c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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Since you're sending a clock to the ADC and getting back data, it is source-synchronous,

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I thought 'source synchronous' meant that the data and the clock are travelling in the same direction, i.e. one receives the sending clock along with the sent data?