Source Synchronous Input Edge Aligned DDR

Being that this is a source synchronous interface, you should use the clock from the A/D to capture the data in the FPGA. You can probably get away with not using a PLL to shift your clock into the center of the data valid window at this frequency. If the inputs are constrained properly, then the programmable delays on the I/Os will take care of shifting the data relative to the clock to meet your setup and hold requirements giving you positive slack.