sorter in vhdl

here is my attempt as guide only:

library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bubblesort is
port(
    clk      : in std_logic;
    we       : in std_logic := '1';
    trigraph : in std_logic_vector(7 downto 0) := x"0F";
    duration : in integer range 0 to 1023 := 5;
    dout     : out std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of bubblesort is
  
signal ram_din, ram_dout : std_logic_vector(8 downto 0) := (others => '0');
type mem is array(0 to 1023) of std_logic_vector(8 downto 0);
signal ram : mem := ((others=> (others=>'0')));
begin
--infer ram
process(clk)
begin
if(rising_edge(clk)) then
   ram_dout <= ram(duration);
   if(we = '1') then
      ram(duration) <= ram_din;
   end if;
end if;
end process;
ram_din <= trigraph & we; 
dout <= ram_dout(8 downto 1);
  
end rtl ; 

notice I use we as flag that a write occurred in case data is zeros all.

after all ram write is done you need to control address (instead of duration) so that you read from address 1023 to 0 to get the code out provided bit(0) of ram_dout is '1'.

I am assuming each code will have its unique duration