SOPC/Quartus II "pass through component" problem

Since my main goal is not only passing data through but also doing some extra work like XORing some of the pixel values etc. later on (it might even get more complex than that), then it makes more sense to stick to your suggestion of keeping the frame buffer in my design and adding my custom passthrough component before that.

Tyler

I have a new question, guys.

Suppose that you want to XOR the actual values of some of the pixels with randomly generated numbers. The desired count of randomly generate numbers should be around 150000 and up but for now 14000 should be ok.

Starting with pixel number 1000, you XOR every pixel's RGB values with a different randomly generated number down to 15000 (considering the scan line).

Can I achieve something like that using my design ? I will consider doing the XORing operation in my dummy pass through component

Can I do this in a considerable time so that it won't give any errors when I compile?

Thanks in advance again,

Tyler

Another problem,

So, the project runs with CVI->frame buffer->CVO

but when I add my new pass through component, all I see is a white screen. Before I changed the auto-generated code, I was seeing a black screen, and after changes I made, I am seeing white screen now. So it is an improvement but still, I am not able to see the actual display as my output.

The code I changed for my custom component is as followed. Am I forgetting something ?

I obviously do :)

// new_component_2.v

// This file was auto-generated as a prototype implementation of a module

// created in component editor. It ties off all outputs to ground and

// ignores all inputs. It needs to be edited to make it do something

// useful.

//

// This file will not be automatically regenerated. You should check it in

// to your version control system if you want to keep it.

module new_component_2 (

input wire clock, // clock.clk

input wire reset, // .reset

input wire ready, // avalon_streaming_source.ready

output wire valid, // .valid

output wire [23:0] data, // .data

output wire startofpacket, // .startofpacket

output wire endofpacket, // .endofpacket

output wire ready1, // avalon_streaming_sink.ready

input wire valid1, // .valid

input wire [23:0] data1, // .data

input wire startofpacket1, // .startofpacket

input wire new_signal_11 // .endofpacket

);

//assign valid = 1'b0;

assign valid = valid1;

//assign startofpacket = 1'b0;

assign startofpacket = startofpacket1;

//assign endofpacket = 1'b0;

assign endofpacket = new_signal_11;

//assign ready1 = 1'b0;

assign ready1 = ready;

//assign data = 24'b000000000000000000000000;

assign data = data1;

// TODO: Auto-generated HDL template

endmodule

And my SOPC design pic is enclosed.