Hello Daixiwen,
thanks for your answer!
I just built a new design with SOPC builder using my own VHDL components and one Altera component (Altera Avalon ST-Sink BFM).
In the SOPC System Generation Tab there is shown "System module logic will be created in VHDL".
But, when running ModelSim there is the following error:
# ALTERA version supports only a single HDL# ** Error: (vsim-3039) C:/Test/sopc_system.vhd(543): Instantiation of 'st_sink_bfm_0' failed.# Region: /test_bench/dut
When opening the project directory there is also a "st_sink_bfm_0.v" file. It's Verilog. Where can I choose to generate this component in VHDL?
I'm sorry, I didn't get it yet..........
Thanks for your assistance!
Best Regards!