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do i need a diffrent ip.sdc for the sopc? Here is my SDC-File for main design:
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Sopc builder should have generated automatically a .sdc file for your system.
You must include it in your Quartus project.
Also make sure your checked the "Timing driven synthesis" in Analysis&Synthesis settings and follow the other guidelines reported by timing optimization advisor.
If all this fails maybe the 144MHz frequency is really too high for your device.
Final note: probably this is not your current problem, but usually you must drive the sdram clock pin with a phase lead relative to clock used by sopc system.
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