Some issues about functional simulation

Thank you for reminding the general VHDL IEEE 1076 rule for default initial values

--- Quote Start ---

If an initial value expression appears in the declaration of a variable, then the initial value of the variable is determined by that expression each time the variable declaration is elaborated. In the absence of an initial value expression, a default initial value applies. The default initial value for a variable of a scalar subtype T is defined to be the value given by T'LEFT. The default initial value of a variable of a composite type is defined to be the aggregate of the default initial values of all of its scalar subelements, each of which is itself a variable of a scalar subtype.

--- Quote End ---

However, Quartus isn't following the rule, except for integer type. As a first point, Quartus doesn't use different synthesis for functional and gatelevel simulation. So it's clear, that STD_LOGIC, as well as all derived composited types (STD_LOGIC_VECTOR, SIGNED and UNSIGNED) can't take a value of 'U' respectively (others => 'U'). These types have '0' as default initial value, according to the default POR state of FPGA registers. Only INTEGER is initialized to 'LEFT, as required by the standard.