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Altera_Forum
Honored Contributor
Honored ContributorSome issues about functional simulation
Hi,all when i do the functional simulation for my projection,i find that some of the initial values of my signals are not cleared to "0".how can i do to clear them? thanks.
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- What makes you think that the integer signals should be initialized to 0 without an explicite initialization? Actually Quartus initializes them apparently to their lower bound. As said, you can use an explicite initialization. I wasn't aware of this particular behaviour with integers that have a negative range, but I'm generally using explicite initialization whenever the initial state of a signal matters. --- Quote End --- Every signal/variable in VHDL initialises to left most unless otherwise told to. This is why std_logic starts off as 'U' as its the first listed in the type definition, integer inits to -2**31, naturals to 0 etc.
