Some issues about functional simulation

You will need to add some sort of reset to the 2nd process. In VHDL, unless specified otherwise, signals and variables default to the left most value. In the case of x_even, x_odd and x_wait, they will initialise to -128. Because 0 is in the middle of the range you will have to manually initialise them like this:

signal x_odd, x_even, x_wait : BITS8 := 0;

Next problem:

Not going to be an issue for simulation, but when you synthesize it you are going to cause timing problems. Do not generate clocks like you have with clk_div2. This is a logic clock and therefore you cannot gauarantee timings. Best to create a clock enable instead of a clock. Then you have the AddPolyphase process sensitive to the standard clk (I dont think you need any other signals in the 2nd process's sensitivity list other than clk).

So like this:

AddPolyphase : process(clk)
begin
     if rising_edge(clk) then
    if clk_div2 = '1' then
      --do variable assignments here, NOT outside the clock 
      --add together r and y values
    end if;
  end if;
end process;