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Altera_Forum's avatar
Altera_Forum
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16 years ago

Some issues about functional simulation

Hi,all when i do the functional simulation for my projection,i find that some of the initial values of my signals are not cleared to "0".how can i do to clear them? thanks.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

It seems to me, the Quartus simulator considers the power on reset of FPGA registers and don't need an explicite initialization. It apparently reflects the real FPGA behaviour.

If some signals aren't reset to '0', they most likely aren't in the synthesized design. Quartus synthesis may have inverted some registers due to hardware constraints, but it will issue a warning in this case.