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Honored Contributor
Honored ContributorSome glitches in the simualtion waveforms
Hi, Experts,
I met a problem in my VHDL code. My algorithm is to cut in the deadtime in the incoming PWM signals and output them. I have 6 incoming PWM signals to switch 6 IGBTs. So, these 6 pwm signals are divided into three pairs: top1 & bot1, top2&bot2 and top3&bot3. I did some simulation for "top1&bot1" (deadtime_1.vhd) and "top2&bot2"(deadtime_2.vhd) pwm signals. But, the result is weird: when I only use top1&bot1, the simulation result is good; when I use both "top1&bot1" and "top2&bot2", there are some glitches in waveforms in the simulation....It looks like the clocks are fighting with each other periodically after some cycles. I attached my vhdl code and simulation results. Please give me some advices... GREATLY APPREICATE YOUR HELP!!!!!14 Replies
Altera_ForumSee the Quartus handbook and text editor template references at http://www.alteraforum.com/forum/showthread.php?t=1025 for coding style guidelines.
- Altera_Forum
If cali_done and start_cal are asynchronous inputs like a reset, add them to the sensitivity list. If they are synchronous inputs, move them inside the "elsif rising_edge (clkin)".
- Altera_Forum
Hi,Brad,
Thanks for pointing out the mistake. Now, I only keep "clkin" in the sensitivity list, but result is the same.... --- Quote Start --- In deadtime_1 you have
The only signals in the process sensitivity list should be the clock and asynchronous control signals like a reset. It looks like you wanted to use pwm_top1_in as a synchronous input to the register. The synchronous inputs should not be in the sensitivity list. --- Quote End ---first_pair: process (clkin, pwm_top1_in) - Altera_Forum
In deadtime_1 you have
The only signals in the process sensitivity list should be the clock and asynchronous control signals like a reset. It looks like you wanted to use pwm_top1_in as a synchronous input to the register. The synchronous inputs should not be in the sensitivity list.first_pair: process (clkin, pwm_top1_in)
