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Altera_Forum
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10 years ago

Some basic questions about DDR

Hi all, I am studying the RTL based example code of LPDDR2 demonstration of Cyclone V 5CGXFC5C6 development kit from Terasic. Basically, this demo code utilizes a LPDDR2 IP, and then w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I just found that if I de-select the "Enable Hard External Memory Interface" in figure "IP Setting_1", then the data width of avl_rdata and avl_wdata will comply with the rule: Full rate -- x2; Half rate -- x4.

If I select this feature, then I can only select "Full rate", and data bus would be 32, the same with DQ width of memory chip.

So, what is going on here?