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A viable and standard solution could be to use ASI protocol over optical interface, it supports up to 270Mbit/s per channel (it's a classical fibre channel application) and you can find ICs (Cypress, Gennum) and IPs (Altera has a complete ASI IP) for that job. In this way you won't have to design your own FW for clock and data recovery.
But indeed you may try to design your own, it is a matter of enough oversampling ratio and some FIFO-aided technique of jitter reduction. It is a very interesting experience to design a CDR block.
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Unfortunately I can not pick the protocol of incoming data - it is given as a requirement. So it seems I'll either have to implement the CDR in the FPGA or get a chip to do that.
There's an interesting AN from Xilinx on CDR implementation with 90 degree shifted PLL clocks:
http://www.xilinx.com/bvdocs/appnotes/xapp224.pdf
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