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MGrub5's avatar
MGrub5
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7 years ago

Soft LVDS aligned output clock

Hello! I am looking for help with a SERDES setup using Quartus. First a brief problem description and then I will provide more details below. The 10-to-1 serializer is driven with two external clock...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
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7 years ago
Hello Marco , Thank you for the detailed explanation , Sorry for late reply , i was caught into other stuff As per the Max 10 LVDS Serdes user guide , fast clock input should connect to the c0 and slow clock connect to the c1, but in your design it is vice versa. Coming back to your question , You can use the loaden signal to mention the receiver your new set of the data begins. isnt it slow clock is already aligned with your data ? I am not sure where iam missing out in your design. thank you , Regards, Sree
MGrub5's avatar
MGrub5
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7 years ago

Hello Sree,

Thank you for your response!

"isnt it slow clock is already aligned with your data ? I am not sure where iam missing out in your design."

The slow clock is correctly aligned with the incoming parallel data.

What I am looking for is some kind of framing signal for the outgoing serialized data (where does the 1st bit of the outgoing stream start?)

When using LVDS Serdes with its own internal PLL it generates an outgoing slow clock. When using LVDS Serdes with the external PLL I do not see any option to get an outgoing clock though