SoC Cyclone V example design : error->hierarchical path is too long

The problem is ghrd_top.v is still the top level in your design (double click it in the heirachy and that's the file that loads). It then instantiates soc_system.bdf but that instantiates ghrd_top.v which is causing the loop.

I think you are confusing symbols and schematics. Symbols are the blocks that show up in the schematic which is described by the .bdf file. I think what you really want to do is enable the symbol generation for the Qsys system, then include that symbol into a larger schematic that includes all the other stuff that's in ghrd_top.v You would make this new schematic the top level of your design instead of ghrd_top.v