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Altera_Forum
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16 years ago

Small device that can deserialize camera data?

Hello all. I am new to Altera devices so excuse my ignorance if this is an obvious question.

I am developing an application that uses an Aptina camera device outputting LVDS image data. I want to feed this data into an FPGA for some minor processing and glue logic duties. I need a device that is around 12mm square (or less).

The camera outputs 12 bit serial packets (10 bit payload plus a start and stop bit) at 324Mhz. So I need a device that can receive at that speed and reconstruct the clock from the data.

It looks like the Cyclone IV EP4CGX15 comes in an 11mm square package and can do clock reconstruction and certainly support that speed. Can this device support the 12 bit format?

James

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I don't see how it can work with Cyclone IV GX. CDR is only available for Gigabit receivers, they don't work at 324 MBps. Unlike Arria II GX, the device has no soft CDR for LVDS receivers.

    Depending on the signal specification, it may be possible however to perform the clock recovery with a simplified soft CDR based on PLL dynamic phase shift with Cyclone III or IV. There's no Altera IP for it, but the feature is present by design. A Cyclone III SERDES has to be built in logic cells, so it's no problem to design it for an abitrary word length.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I know I'm resurrecting a 3 year old thread here, but I'm looking at doing the same thing using a Stratix IV GX. I expect the ALTLVDS_RX megafunction can be used with a deserialization factor of 6 with the two 6-bit nibbles combined to produce the 12-bit output. I'm hoping the DPA and soft-CDR blocks can still be used in this type of setup. Does that sound right?

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    may be you can use one PLL to generate the clock to sample the incoming LVDS data

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    What image sensor are you looking at? You probably can get away without using DPA or soft-CDR

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    MT9V034.

    I'm implementing the ALTLVDS_RX with a deserialization factor of 6 and registering the two consecutive 6-bit nibbles to create 12-bit words. I'm simulating in ModelSim using a training pattern and it appears to lock on with good word alignment, but then I'll see a single corrupted word followed by a bit alignment problem. Pulsing the rx_channel_data_align port several times I see the bit alignment shift left, but then rolls over and skips a bit alignment and goes back to the bad alignment. I suspect the DPA switched the sample clock when I received the corrupted word and now I can't get it to align. To better illustrate what I'm seeing, I'm expecting the following pattern "000101110101", but received "001011101010". Each pulse of rx_channel_data_align shifts the pattern left by a bit until I get to "101010001011", then on the next pulse I'm back to "001011101010". It could be that I've hit my "data_align_rollover" parameter which is currently set to 6. The datasheet/user guide seems to imply that this can be set higher than the deserialization factor...
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Changing the "data_align_rollover" parameter to 11 allows me to use bit slip to align the data, but it keeps blipping and requiring realignment every 218us or so. That's obviously not going to work for video.

    I'm going to add some logic to keep a count of the number matching words with good alignment and then assert the "rx_dpll_hold" port to prevent it from switching clocks.