New Contributor
New ContributorCheePin
I do handle the byte ordering.
I believe my issue lies in the interaction between the Native PHY and the Reset Controller IP that I used.
I am watching that with SignalTap now.
Will get back to you with what I see.
New ContributorChee Pin
I have been looking at the Reset signals from the Reset Controller and it looks like there is some difficulty with the lanes locking to data (rx_is_lockedtodata signal goes false).
Digging into this now.
I have included my nativephy.v per your request.
New ContributorChee Pin
Could you comment on the clocks I am using in my interface?
The Native PHY is clocked at 74.25 MHz (cdr_refclk) which is one of the choices given in the Megawizard when building the core. My input data rate per lane is 2376 Mb. 2376M/32 = 74.25M.
I have been clocking the Reset Controller at that same rate (74.25 MHz).
I have been clocking the Reconfig Controller at 100 MHz.
Should the Reset Controller and Reconfig Controller run on same clock?
